Recently, many photonic Ising machines for solving combinatorial optimization problems (COPs) based on various physical platforms have been reported, but the implementation of high-dimensional and integrated photonic Ising machines is still challenging. In this work, we demonstrated a 16-channel photonic solver for COPs based on a silicon photonic chip with Chongqing United Microelectronics Center. The chip integrates 16 high-speed electro-optic modulators, an MZI array, and 16 balanced photodetectors to perform low-latency optical vector-matrix multiplications, and searches for the near-optimal solutions along with the FPGA (Field programmable gate array) which conducts the heuristic algorithms. In the experimental demonstration, two randomly generated 16-dimensional quadratic unconstrained binary optimization problems are solved, in which high transformation stability (average fidelity > 0.99) and high successful probability (close to 1 when the tolerance coefficient ≤ 0.98). Besides, the average sampling iteration for each state is 265.1 ns. The computing speed of the photonic chip is estimated to be 1.66 TFLOP/s according to the bandwidth of the modulators and the photodetectors. This research exhibits the potential of the integrated photonic systems to accelerate the solving process of computationally complex problems.

This research entitled “16-channel photonic solver for optimization problems on a silicon chip” was published on the journal “Chip” on November 8th, 2024 (https://doi.org/10.1016/j.chip.2024.100117). PhD. Jiayi Ouyang is the co-first author. Prof. Xue Feng and Prof. Yidong Huang are the corresponding authors.